Digital communication systems (DCS) incorporating, asynchronous, serial digital data signals typically transmit and receive bytes of information with the use of a universal asynchronous receiver/transmitter (UART). The digital signals are transmitted back and forth using a framing format. The framing format determines such bits in a byte as the number of data bits, parity bits and stop bits. The parity bits are used for error detection and the stop bits allow for a minimal idle interval so that subsequent bytes can be detected. To achieve successful communication between UARTs, the speed of the transmission signals sent back and forth must match. If the speeds are different, framing and parity errors can occur that will result in invalid communication between the two devices.
To assure proper matching of speeds between UARTs, it is desirable to allow one UART to dynamically match the speed of the other UART. Since a number of known speeds exits, a UART could simply cycle through known speeds upon receiving a signal until a match is found. Unfortunately, this could be a time consuming process. An alternative approach could be to use software to attempt to match bytes with known patterns. This approach, however, is slower and more complicated.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved device and method of matching communication speeds.